Field
Aspects of the present disclosure relate generally to power control for system-on-a-chip integrated circuits, and more particularly, to a method and apparatus for hybrid chip-level voltage scaling.
Background
In a battery powered device, being able to reduce power consumption in order to extend battery life is of significant importance. One component that consumes a significant portion of the power budget, referred to as a system-on-a-chip (SoC), is an integrated circuit (IC) that combines many, if not all, functional subsystems of a computer or other electronic system into a single chip. For example, a SoC may include not only a processor, but also include memory (both volatile and non-volatile), interfaces (including those for peripherals, and networks), voltage regulators, timers, and any other application-specific circuits that may be integrated by design. These various subsystems may share a common power rail. The SoC is set to operate at specified voltages based on predetermined conditions. In other words, an operating voltage for the shared power rail is statically determined based on an aggregation of requirements for the various subsystems for each particular operating profile. A static mapping may thus be determined between each operating profile of the SoC and its required operating voltage and clock frequency. To reduce power consumption in typical SoC implementations, a SoC may be placed in a sleep mode—during which it consumes very little power. The SoC may also be placed in an idle mode, which is a mode of operation that allows the SoC to return into an active mode faster, but which consumes more power than the sleep mode.
While a lot of work has been done to reduce power consumption in idle or sleep modes, dynamically adjusting power consumption to meet performance and power targets when the system is being used has been relatively neglected. Because energy consumption is a product of power and time, with power being proportional to the square of the voltage, the ability to dynamically adjust an operating voltage level when the SoC is active is very desirable because an exponential reduction of energy consumption is possible based on a reduction of just the voltage component. Considering the fact that the device may be active for the entire duration that the battery is capable of powering the device, having this capability is even more desirable.
Further, due to manufacturing tolerances that result in differences in the manufactured chips, operating conditions for SoCs may fluctuate from chip to chip. Statically determined power profiles may not be optimized for these differences, but instead are forced to provide a safe voltage level for each power profile that may be applied to all SoCs for which these profiles are determined. Thus, the safe voltage level for a particular power profile must be as least as high as a minimal voltage level for a worst-case scenario that may be experienced by any device for which the particular power profile is designed. Otherwise, the SoC will not function properly or may even be damaged. As an extremely simplified example, assume that there are only two possible variations in manufacturing tolerances for a SoC that results in a first type of SoC needing a first voltage level to operate at a particular clock frequency, while a second type of SoC may require a second voltage level to operate at the same clock frequency. Assume further that the second voltage level is higher than the first voltage level. If the profile that is statically determined for both of these types of SoCs at the particular clock frequency are at the first voltage level, then all SoCs of the second type may fail to properly perform or even be damaged as they are not provided with a voltage level that is at least as high as the second voltage level. Although it has been proposed that profiles may be determined on a device-by-device basis, this approach would significantly reduce manufacturing throughput as well as increase design complexity for production.
Thus, it would be desirable to be able to address the issues identified above to be able to provide significant increased operating time for devices while not reducing performance significantly.